The Densmore Manifesto v2.0

On June 20th, 2008 Erika and I got married. It was a super hot day but the ceremony was great and we had a blast. My brother Luke was my best man and Erika’s sister Monica was her maid of honor. My nephew Zach was the ring bearer and my cousin’s daughter, Sierra, was the flower girl. My sister read a poem she wrote and the officiant was my friend Steve’s dad. It was a lot fun seeing all my friends and family in one place and all dressed up. The whole thing was a blur but we made some great memories (and took some great photos).

I received my PhD in Electrical Engineering here at Berkeley after 6+ years of grad school on May 18th, 2007. Immediately after graduating my mom, Erika, and I went to Japan to visit my sister Diana. We had a good time and I am glad to be back in the states. For the next year or two I will be a post doc researcher at Berkeley. I will be working on refinement verification, architecture modeling, and model alegbra. I am currently receiving the UC Chancellor’s Post Doctoral fellowship and would like to find academic employment when I am done at Berkeley.

Hello and welcome to the website of Douglas Densmore. The purpose of this website is to provide information about myself.

I was born in Kalamazoo, MI and attended both Gull Lake High School and the Kalamazoo Area Mathematics and Science Center. After high school I attended the University of Michigan where I graduated in April 2001 with a degree in Computer Engineering. I received my masters degree in Electrical Engineering at the University of California, Berkeley in May 2004. I am currently working on my PhD in Electrical Engineering with an expected graduation date of May 2007. Specifically I am majoring in CAD for VLSI. I am a member of Alberto Sangiovanni-Vincentelli’s research group and am a member of the Gigascale Systems Research Center (GSRC) and the Center for Hybrid and Embedded Software Systems (CHESS). My research interests are in system level design of embedded systems, computer architecture, digital logic design and design-for-test.